A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio

Recently, time amplifiers are used in time-to-digital converters (TDC) because the time resolution is better than the voltage resolution in modern integrated circuits. However, the conventional time amplifiers are limited in their time gain and input time difference range, because of their positive-feedback closed-loop architecture. An open-loop time amplifier is proposed in this work to achieve a large time gain up to 120 and a wide range of input time difference(10ps~2ns). Besides, the time gain is the same as the current bias ratio. The worst-case average gain error which shows linear characteristics of the time amplifier is smaller than 5.3% The proposed time amplifier was successfully used in the monitoring circuit for threshold voltage variations of NMOS and PMOS FETs. The monitoring circuit consists of VCDL, time amplifier and TDC. The circuit was implemented by 0.13μm CMOS process.