Modelling and computing the electrical parameters of a multichip module interconnections

In this paper, the network analog method is developed with a view to applying it to compute quasi-static electrical parameters (matrices of capacitance [Cij], inductance [Lij], conductance [Gij] and resistance [Rij]) of multilayer structures in CMOS technology. Finite-difference method with variable increments is applied to solve Laplacepsilas equation. It involves constructing a network analog having complex or real branches. Hence, if any advantages can be obtained, one may solve a network problem using the network analog method instead of the corresponding Laplacepsilas difference equations. Thus, the number of equations, the computational time and the memory space will be considerably reduced. Sample results are presented for conductor line sizes and spacing typical of multilevel VLSI structures.