A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation

Author

Yu, Bei ; Chen, Chixiao ; Zhu, Yu ; Zhang, Peng ; Zhang, Yiwen ; Zhu, Xiaoshi ; Ye, Fan ; Ren, Junyan

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2011

fDate

14-16 Nov. 2011

Firstpage

349

Lastpage

352

Abstract

A 14-bit 200-MS/s time-interleaved analog-to-digital converter (TI-ADC) is presented. An adaptively-controlled sampling switch is proposed to correct the sample-time error between two interleaved channels and an auto-correlation-based sample-time error detection algorithm is introduced to detect the sample-time error. A prototype ADC is fabricated in a 0.18-μm mixed-signal CMOS process with a power consumption of 460 mW from a 1.8-V supply. The ADC achieves an SNDR of 68.5 dB and an SFDR of 88.5 dB for a 15.33MHz input.

Keywords

CMOS integrated circuits; adaptive control; analogue-digital conversion; mixed analogue-digital integrated circuits; SFDR; SNDR; TI-ADC; adaptively-controlled sampling switch; autocorrelation-based sample-time error cancelation algorithm; autocorrelation-based sample-time error detection algorithm; frequency 15.33 MHz; interleaved channel; mixed-signal CMOS process; noise figure 68.5 dB; noise figure 88.5 dB; power 460 mW; power consumption; size 0.18 mum; time-interleaved analog-to-digital converter; voltage 1.8 V; word length 14 bit; CMOS integrated circuits; Calibration; Capacitors; Clocks; Linearity; Switches; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4577-1784-0

Type

conf

DOI

10.1109/ASSCC.2011.6123586

Filename

6123586