DocumentCode
2940289
Title
A time-domain architecture and design method of high speed A-to-D converters with standard cells
Author
Takayama, Masao ; Dosho, Shiro ; Takeda, Noriaki ; Miyahara, Masaya ; Matsuzawa, Akira
Author_Institution
Digital-Core Dev. Center, Panasonic Corp., Moriguchi, Japan
fYear
2011
fDate
14-16 Nov. 2011
Firstpage
353
Lastpage
356
Abstract
In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier(TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter(SA-TDC). The test chip includes 8 interleaved 4bit SA-TDCs with short latency. The chip operates up to 4.4GHz. The measured ENOB is 3.51bit and FOM is 0.49pJ/conv.
Keywords
time-digital conversion; analog signal; clock edge; design method; speed A-to-D converters; standard cells; successive approximation time-to-digital converter; time amplifier; time-domain architecture; time-interleaved phase modulation signal; voltage signal; word length 3.51 bit; word length 4 bit; Clocks; Delay; Inverters; Linearity; Logic gates; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location
Jeju
Print_ISBN
978-1-4577-1784-0
Type
conf
DOI
10.1109/ASSCC.2011.6123587
Filename
6123587
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