• DocumentCode
    2940307
  • Title

    Chaitali Chakrabarti

  • Author

    Chakrabarti, Chaitali

  • Author_Institution
    Department of Electrical Engineering,Arizona State University,Tempe, AZ, USA
  • fYear
    1992
  • fDate
    28-30 Oct. 1992
  • Firstpage
    490
  • Lastpage
    499
  • Abstract
    This paper presents high sample rate array architectures and sorting network-based architectures for computing both recursive and non-recursive median filters. The proposed array architectures have a sampling rate that is higher than that of existing architectures. This is achieved by pipelining the computations in each processor. While the non-recursive filters are pipelined by placing latches in the feed-forward paths, the recursive filters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches. The proposed sorting network-based architectures are highly pipelined, and consist of fewer compare-swap units than existing architectures. The reduction in the number of compare-swap units is achieved by processing multiple outputs at the same time, and also by using Batcher´s odd-even merge sort. The latency of these networks is reduced by building them with sorting units which sort 2 elements (sort-2) as well as 3 elements (Sort-3) in 1 time unit.
  • Keywords
    Added delay; Computer architecture; Computer networks; Digital filters; Feedback; Feedforward systems; Filtering; Nonlinear filters; Pipeline processing; Sorting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Signal Processing, V, 1992., [Workshop on]
  • Conference_Location
    Los Angeles, CA
  • Print_ISBN
    0-7803-0811-5
  • Type

    conf

  • DOI
    10.1109/VLSISP.1992.641080
  • Filename
    641080