A DSP-based implementation of a turbo-decoder

Author

Blazek, Z. ; Bhargava, V.K.

Author_Institution

Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada

Volume

5

fYear

1998

fDate

1998

Firstpage

2751

Abstract

This paper focuses on a DSP based implementation of a decoder for a simple turbo-code, consisting of two constituent codes of constraint length three and a 192 bit block interleaver. With three full iterations of the SOVA-based turbo-decoder executing on a single DSP chip, a data rate of approximately 10 kbps can be achieved. This implementation is then compared against a Viterbi decoder for the “NASA standard” constraint length seven convolutional code

Keywords

AWGN channels; Rayleigh channels; Viterbi decoding; digital signal processing chips; interleaved codes; iterative decoding; turbo codes; 10 kbit/s; 192 bit; AWGN channels; DSP-based implementation; NASA standard; Rayleigh fading channels; SOVA-based turbo-decoder; Viterbi decoder; block interleaver; code constraint length; constituent codes; convolutional code; data rate; iterations; single DSP chip; turbo-decoder; AWGN; Bit error rate; Convolutional codes; Digital signal processing chips; Error correction codes; Iterative decoding; Performance analysis; Turbo codes; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1998. GLOBECOM 1998. The Bridge to Global Integration. IEEE

Conference_Location

Sydney,NSW

Print_ISBN

0-7803-4984-9

Type

conf

DOI

10.1109/GLOCOM.1998.776488

Filename

776488