System performance and energy consumption improvement methodology by delay adjustable synchronizer

We propose a novel synchronizer and design methodology which control the probability of metastability quantitatively by a tunable delay and relax the data rate constraint due to the conventional synchronizer. They improve system performance and reduce energy consumption. We applied our synchronizer and methodology for two types of designs, a digital signal processor and a microprocessor. The former design consists on a unidirectional data flow by the asynchronous interface. Our methodology improves system performance by 43% and reduces total energy consumption by 37%. The latter design consists on CPU core whose frequency is fixed, and the system performance depends on the operating speed of the core. Even such a design, our methodology reduces total energy consumption by 9% keeping the same system performance. In addition, both designs have no area penalty.