A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators

Author

Wong, Si-Seng ; Chio, U-Fat ; Chan, Chi-Hang ; Choi, Hou-Lon ; Sin, Sai-Weng ; Seng-Pan, U. ; Martins, R.P.

Author_Institution

State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China

fYear

2011

fDate

14-16 Nov. 2011

Firstpage

73

Lastpage

76

Abstract

This paper presents a topology to improve the system linearity and reduce the complexity of high-speed binary-search ADCs. The proposed topology, when compared with previous binary-search ADC architectures, further reduces the number of comparators from 2N-1 to N for N-bit precision, the comparator structure is simplified, and it can avoid both the signal dependent offsets and the kickback noise. The proposed binary-search ADC has been implemented in 65nm CMOS process and it consumes 1.63mW at an operation frequency of 500MS/s. The measurement results demonstrate that the binary-search ADC achieves 30.7dB SNDR (4.8-bit ENOB).

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; circuit complexity; comparators (circuits); integrated circuit noise; network topology; search problems; CMOS process; ENOB binary-search ADC; N-bit precision; analog-to-digital converter; binary-search ADC architecture; comparator structure; complexity reduction; high-speed binary-search ADC; kickback noise; network topology; power 1.63 mW; size 65 nm; system linearity; word length 4.8 bit; CMOS integrated circuits; Calibration; Clocks; Noise; Quantization; Signal resolution; Voltage control; Analog-to-Digital Converter (ADC); SAR ADC; asynchronous binary-search ADC; flash ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4577-1784-0

Type

conf

DOI

10.1109/ASSCC.2011.6123607

Filename

6123607