DocumentCode
2940871
Title
3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS
Author
Lee, I-Ting ; Wang, Chiao-Hsing ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2011
fDate
14-16 Nov. 2011
Firstpage
93
Lastpage
96
Abstract
Two 3.6mW D-band divide-by-3 injection-locked frequency dividers (ILFDs) are realized in a 65nm CMOS process. The power consumption is 3.6mW for a supply of 1.2V. By using a second-harmonic enhancement technique, a divide-by-3 ILFD achieves a locking range of 130.01~132.4GHz. To the authors´ best knowledge, this is the first divide-by-3 CMOS ILFD to work at D band.
Keywords
CMOS analogue integrated circuits; frequency dividers; CMOS process; D-band divide-by-3 ILFD; D-band divide-by-3 injection-locked frequency divider; frequency 130.01 GHz to 132.4 GHz; power 3.6 mW; power consumption; second-harmonic enhancement technique; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Frequency measurement; Inductors; Mixers; Oscillators; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location
Jeju
Print_ISBN
978-1-4577-1784-0
Type
conf
DOI
10.1109/ASSCC.2011.6123612
Filename
6123612
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