Design and demonstration of micro-electro-mechanical relay multipliers

This paper describes the micro-architecture and circuit techniques for building multipliers with micro-electromechanical (MEM) relays. By optimizing the circuits and micro-architecture to suit relay device characteristics, the performance of the relay based multiplier is improved by a factor of ~8× over any known static CMOS-style implementation, and ~4× over CMOS pass-gate equivalent implementations. A 16-bit relay multiplier is shown to offer ~10× lower energy per operation at sub-10 MOPS throughputs when compared to an optimized CMOS multiplier at an equivalent 90 nm technology node. To demonstrate the viability of this technology, we experimentally demonstrate the operation of the primary multiplier building block: a full (7:3) compressor, built with 98 MEM-relays, which is the largest working MEM-relay circuit reported to date.