Title :
A leakage-current-recycling phase-locked loop in 65nm CMOS technology
Author :
Lee, I-Ting ; Tsai, Yun-Ta ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider and a dual-mode phase-frequency detector. This PLL is fabricated in a 65nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640MHz are 52.2ps and 9.6ps, respectively. Its power consumption is 1mW for a 1.2V supply voltage.
Keywords :
CMOS integrated circuits; MOS capacitors; dividing circuits; leakage currents; phase detectors; phase locked loops; voltage-controlled oscillators; PMOS capacitor; divider; dual-mode phase-frequency detector; frequency 640 MHz; leakage-current-recycling PLL; leakage-current-recycling phase-locked loop; nanoscale CMOS technology; peak-to-peak jitter measurement; power 1 mW; power consumption; rms jitter; size 65 nm; time 52.2 ps; time 9.6 ps; voltage 1.2 V; voltage-controlled oscillator; Capacitors; Frequency measurement; Jitter; Leakage current; Phase locked loops; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-1784-0
DOI :
10.1109/ASSCC.2011.6123621
