Title :
A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface
Author :
Yun, Won-Joo ; Ishikuro, Hiroki ; Kuroda, Tadahiro
Author_Institution :
Dept. of EEE, Keio Univ., Yokohama, Japan
Abstract :
An all-digital CDR for a pulse-based inductive-coupling interface is presented, which uses a TDC with free running oscillator for seamless oversampling and an all-digital DLL. The TDC utilizes an error correction scheme to reject noise pulses and the DLL recovers the phase information based on a 32-bit digital comparator. Peak-to-peak jitter is 12.2ps with 1.2Gb/s at 1.2V, whereas energy consumption is 4.7pJ/b with 1.2Gb/s at 0.6V.
Keywords :
circuit noise; clock and data recovery circuits; comparators (circuits); coupled circuits; error correction; jitter; low-power electronics; oscillators; time-digital conversion; all-digital DLL; bit rate 1.2 Gbit/s; clock and data recovery circuit; digital comparator; energy consumption; error correction scheme; free running TDC; free running oscillator; noise pulse rejection; noise rejectable all-digital CDR; peak-to-peak jitter; phase information; pulse-based inductive coupling Interface; seamless oversampling; time-to-digital converter; voltage 0.6 V; voltage 1.2 V; word length 32 bit; Clocks; Couplings; Delay; Detectors; Error correction; Image edge detection; Noise;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-1784-0
DOI :
10.1109/ASSCC.2011.6123623
