A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM

Author

Lee, Jong-Chern ; Jin, Sin-Hyun ; Kim, Dae-Suk ; Ku, Young-Jun ; Kim, Chul ; Park, Byung-Kwon ; Kim, Hong-Gyeom ; Ahn, Seong-Jun ; Lee, Jae-Jin ; Hong, Sung-Joo

Author_Institution

TSV Technol. Dev. Team, Hynix Semicond. Inc., Icheon, South Korea

fYear

2011

fDate

14-16 Nov. 2011

Firstpage

157

Lastpage

160

Abstract

This paper presents a low-power small-area open loop digital DLL. The DLL has open loop single replica block with duty cycle corrector (DCC), clock divider, pulse generator, 10-bit counter, and delay line. The DLL used for 2.2Gb/s/pin 2Gb DDR3 SDRAM is fabricated using 44nm DRAM Process. Experimental results show 1.1GHz operation frequency at 1.5V, and the measured total power and area savings in comparison with the conventional closed-loop operation is about 93.5% and 90.7% respectively.

Keywords

DRAM chips; clocks; counting circuits; delay lines; delay lock loops; dividing circuits; low-power electronics; pulse generators; DCC; DDR3 SDRAM; bit rate 2.2 Gbit/s; clock divider; counter; delay line; duty cycle corrector; low-power small-area open loop digital DLL; open loop single replica block; pulse generator; size 44 nm; voltage 1.5 V; word length 10 bit; Clocks; Delay; Delay lines; Jitter; Power demand; Pulse generation; SDRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4577-1784-0

Type

conf

DOI

10.1109/ASSCC.2011.6123626

Filename

6123626