An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation

Author

Niitsu, Kiichi ; Sakurai, Masato ; Harigai, Naohiro ; Yamaguchi, Takahiro J. ; Kobayashi, Haruo

Author_Institution

Dept. of Electron. Eng., Gunma Univ., Kiryu, Japan

fYear

2011

fDate

14-16 Nov. 2011

Firstpage

201

Lastpage

204

Abstract

This paper demonstrates a reference-free, high-resolution on-chip timing jitter measurement circuit. It combines a self-referenced clock and a cascaded time difference amplifier (TDA) with duty-cycle compensation, which results in reference-free, high-resolution timing jitter measurement without sacrificing operational speed. The test chip was designed and fabricated in 65 nm CMOS. Measured results of the proposed circuit show the possibility of detecting a timing jitter of 1.61-ps RMS in 820 MHz clock with less than 4% error.

Keywords

CMOS analogue integrated circuits; amplifiers; clocks; integrated circuit design; timing circuits; CMOS technology; TDA; cascaded time difference amplifier; chip design; duty-cycle compensation; frequency 1 MHz; on-chip timing jitter measurement circuit; self-referenced clock; size 65 nm; timing jitter detection; Clocks; Delay; Frequency measurement; Semiconductor device measurement; System-on-a-chip; Timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4577-1784-0

Type

conf

DOI

10.1109/ASSCC.2011.6123637

Filename

6123637