• DocumentCode
    2941688
  • Title

    The Second Generation Intel® Core™: A highly integrated high performance multi IA-core and processor graphics chip

  • Author

    Yuffe, Marcelo ; Vikinski, Omer ; Shmuely, Ziv ; Knoll, Ernest ; Kurts, Tsvika

  • Author_Institution
    Intel Corp., Haifa, Israel
  • fYear
    2011
  • fDate
    14-16 Nov. 2011
  • Firstpage
    13
  • Lastpage
    16
  • Abstract
    This paper describes the Second Generation Intel® Core™ processor, a 32nm monolithic die integrating four IA cores, a processor graphics and a memory controller. The die was designed for high performance but without compromising the part power consumption or the part and system cost. To achieve these targets a modular design methodology was devised, this methodology allows fast configuration of the die to achieve the optimal performance/cost/power point for a specific market segment. In this paper some of the techniques used to control the die and package cost are described. Special attention is given to debug-ability hooks that considerably reduce the system time-to-market of this kind of highly integrated processors.
  • Keywords
    graphics processing units; time to market; debug-ability hooks; die control; highly-integrated processors; integrated high-performance multiIA-core; memory controller; modular design methodology; monolithic die; package cost control; processor graphics chip; second-generation Intel core; system time-to-market reduction; Graphics; Microprocessors; Mobile communication; Process control; Protocols; Routing; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4577-1784-0
  • Type

    conf

  • DOI
    10.1109/ASSCC.2011.6123652
  • Filename
    6123652