Design of a 12-Channal 120-Gb/s Optical Receiver Front-End Amplifier in 0.18-im CMOS Technology

A 12-channal 120-Gb/s optical receiver front-end amplifier array has been designed in a 0.18-μm CMOS process. This front-end amplifier array incorporates transimpedance amplifiers (TIAs) and limiting amplifiers (LAs). A regulated cascode (RGC) input structure, active inductor peaking and feedback technique are exploited to enhance the bandwidth without deterioration of the other performances. And a novel noise analysis and optimization method was proposed to drive the front-end amplifier to obtain good noise performance. An isolation structure combined with P⁺ guard-ring (PGR), N⁺ guard-ring (NGR), and deep-n-well (DNW) for parallel amplifiers is employed to reduce the crosstalk and suppress the substrate noise coupling effectively. Post-layout simulations demonstrate that a single channel optical receiver front-end amplifier achieves conversion gain of 93 dBΩ, -3-dB bandwidth of 8 GHz for 0.5-pF photodiode capacitance, and -14.2-dBm optical sensitivity for the photodiode responsivity of 0.52 A/W. By properly adopting the proposed noise optimization method, the optimized average equivalent input noise current per channel is about 2.7 μA_rms. Operating under a 1.8-V supply, the total power dissipation of 12-channel front-end amplifier array is about 1 W, and the chip size is 1142 μm × 3816 μm.