ASIC automatic layout generation using large standard cell libraries

We present an automatic layout generation methodology for ASICs utilizing large standard cell libraries. We also present a complete study of layout area and circuit performance as a result of utilizing a large library of standard cells. We built libraries of all possible static CMOS cells having a chain length of up to 7. We refer to a library of all possible cells having a chain length limit of n as sn. Although Library s7 has billions of possible cells in it, our technology mapper only selected on the order of 100 of these cells to implement each of the MCNC logic synthesis benchmark circuits. We drew the following conclusions from this study. (1) For three or more layers of metal, using very large libraries (e.g., s7) is optimal in terms of area and delay. (2) For two layers of metal, limiting the library size to s5, but at least s4, is optimal in terms of area and delay. Given that the number of distinct combinational cells in industrial libraries today never exceeds 200 (and usually considerably fewer) and given that even library s4 has 3503 distinct cells, tremendous area savings (without increase in worst case path delay) are readily available by utilizing much larger cell libraries. Specifically, given that library s3 has 87 distinct cells (current industrial libraries typically have no more than this), we surmise that area savings of about 30% can be achieved by using library s7 for three or more metal layers versus any current industrial library