Extraction of an extrinsic parasitic network for accurate mm-Wave FET scalable modeling on the basis of Full-Wave EM simulation

This paper describes a new methodology for the extraction of an extrinsic parasitic network suitable for scalable electron device models. The extraction procedure is based on the data obtained through full-wave electro-magnetic (FW-EM) analyses of the passive structure of a reference device. The new topology proposed proves to be scalable according to simple linear rules derived from geometric considerations. This new parasitic network is used together with a scalable intrinsic device model in order to predict the behavior of different 0.25 mum GaAs PHEMTs (total gate-widths between 300 and 900 mum) belonging to a standard process for millimeter-wave applications. Better accuracy with respect to conventional modeling approaches, is proved up to 80 GHz.