A new single-poly flash memory cell with low-voltage and low-power operations for embedded applications

Author

Min-Hwa Chi ; Bergemont, A.

Author_Institution

Adv. Technol. Group, Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1997

fDate

23-25 June 1997

Firstpage

126

Lastpage

127

Abstract

Discusses a new single-poly flash memory cell structure on triple-well CMOS technology and new program/erase schemes with operating voltage not exceeding /spl plusmn/V/sub cc/. Conventional single-poly EPROM, although fully compatible with standard CMOS fabrication, suffers from high-voltage operation, slow programming, and incapability of electrical erase. This new flash cell and program/erase schemes are promising for low-voltage and low-power nonvolatile memory applications in CMOS mixed-signal circuits of system-on-a-chip.

Keywords

CMOS memory circuits; EPROM; cellular arrays; integrated circuit design; mixed analogue-digital integrated circuits; embedded applications; low-power operation; low-voltage nonvolatile memory applications; low-voltage operation; mixed-signal circuits; operating voltage; program/erase schemes; single-poly flash memory cell; system-on-a-chip; triple-well CMOS technology; CMOS logic circuits; CMOS technology; Channel hot electron injection; Coupling circuits; EPROM; Flash memory cells; Implants; Nonvolatile memory; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference Digest, 1997. 5th

Conference_Location

Fort Collins, CO, USA

Print_ISBN

0-7803-3911-8

Type

conf

DOI

10.1109/DRC.1997.612499

Filename

612499