Automatic design of parallel implementations of DSP algorithms

An integrated system is presented combining a rule-based symbolic code simplification system and a fine-grain code scheduler for a multiprocessor based on a ring/mesh of commercial single-chip digital signal processing (DSP) processors. The code simplification component uses a priori information to direct the application of symbolic simplification rules to local or global code segments of the original program. The code generation includes graph parsing, optional blocking, and code scheduling with partial backtracking. Resource allocation is incorporated with operation scheduling to increase the total performance of the practical system. The integrated system can implement many DSP algorithms, generating very efficient code for a variety of DSP processor configurations