Cluster-based placement for macrocell gate arrays

The growing complexity of integrated circuits poses new challenges to the existing layout design tools. This paper presents a modified clustering approach for macrocell gate array placement. Both connectivities and sizes of cells are taken into account in the clustering process. When combined with Generalized Force Directed Relaxation method, the algorithm generates promising results with O(Knlogn) time, where K is the number of clusters and n is the number of cells. Examples are also given to demonstrate the effectiveness of the algorithm