• DocumentCode
    2945283
  • Title

    A new process and tool for metal/high-к gate dielectric stack for sub-45 nm CMOS manufacturing

  • Author

    Venkateshan, A. ; Singh, R. ; Poole, K.F. ; Senter, H.

  • Author_Institution
    Clemson Univ., Clemson
  • fYear
    2007
  • fDate
    15-17 Oct. 2007
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper we report the results of a new process and tool to deposit metal/high-kappa gate dielectric stack. Hafnium oxide dielectric of 0.39 nm EOT is deposited using monolayer photo-assisted deposition process on a home-built system to provide a reliable and robust process to tackle the needs of the future CMOS generations. We report the results of 0.39 nm EOT gate dielectric material with a leakage current density value of about 1 times 10-12 A/cm2 for gate voltage from +3 V to -3 V. The data presented in this paper demonstrate that the process is robust and manufacturing tools can be developed without any fundamental barrier.
  • Keywords
    CMOS integrated circuits; chemical vapour deposition; integrated circuit manufacture; monolayers; CMOS manufacturing; hafnium oxide dielectric; home-built system; metal/high-k gate dielectric stack; monolayer photo-assisted deposition process; size 0.39 nm; size 45 nm; voltage 3 V; CMOS process; Cleaning; Costs; Dielectrics; Hafnium oxide; Leakage current; Manufacturing processes; Pulp manufacturing; Robustness; Water;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1523-553X
  • Print_ISBN
    978-1-4244-1142-9
  • Electronic_ISBN
    1523-553X
  • Type

    conf

  • DOI
    10.1109/ISSM.2007.4446871
  • Filename
    4446871