Title :
Yield considerations in the choice of 3D technology
Author :
Smith, Greg ; Smith, Larry ; Hosali, Sharath ; Arkalgud, Sitaram
Author_Institution :
SEMATECH, Austin
Abstract :
Die-to-wafer (DtW) stacking offers a yield advantage over wafer-to-wafer (WtW) and system-on-a-chip (SoC) if testing can identify good die and reduce stacking of good and bad die pairs. In this study, an SoC is broken into two equal areas to form a 3D system, and best case yields of DtW and WtW is compared. Testing need not be perfect to realize significant yield advantage with DtW.
Keywords :
logic testing; system-on-chip; 3D technology; SoC; die-to-wafer stacking; CMOS technology; Delay; Face; Paper technology; Semiconductor device modeling; Stacking; Statistics; System testing; System-on-a-chip; Wafer bonding;
Conference_Titel :
Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-1142-9
Electronic_ISBN :
1523-553X
DOI :
10.1109/ISSM.2007.4446880
