A flexible layered LDPC decoder

We introduce a flexible layered decoder architecture for Quasi-Cyclic Low Density Parity Check (LDPC) codes. An iterative construction of the parity check matrix is exploited by the proposed decoder to achieve various degrees of parallelism, characterized by a high utilization of variable and check processing nodes, absence of memory conflicts, and a simple and scalable interconnection network. Furthermore, the proposed LDPC decoder supports variable code rate, information-word length and order of modulation. A comparison to prior-art decoders proves the efficiency of the proposed scheme.