Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors

To date dynamic voltage/frequency scaling (DVFS) has been one of the most successful power-reduction techniques. However, ever-increasing process variability reduces the reliability of static random access memory (SRAM) at low voltages. This limits voltage scaling to a minimum operating voltage (V_DDMIN). Larger SRAM cells, that are less sensitive to process variability, allow the use of lower V_DDMIN. However, large-scale memory structures, e.g., the last-level cache (LLC) (that often determines the V_DDMIN of the processor), cannot afford to use such large SRAM cells due to the die area constraint. In this paper we propose low-voltage LLC architectures that exploit 1) the DVFS characteristics of workloads running on high-performance processors, 2) the trade-off between SRAM cell size and V_DDMIN, and 3) the fact that at lower voltage/frequency operating states the negative performance impact of having a smaller LLC capacity is reduced. Our proposed LLC architectures provide the same maximum performance and V_DDMIN as the conventional architecture, while reducing the total LLC cell area by 15%-19% with negligible average runtime increase.