Complexity reduced odd-order memory polynomial pre-distorter for 400-watt multi-carrier Doherty amplifier linearization

This paper expounds on the computation complexity reduction of memory polynomial (MP) digital predistorter (DPD) construction and implementation as needed to linearize power amplifiers (PA) when driven with multi-carrier signals. For that, the even-order terms in the MP branches were first removed. Then, the PA memory effects theory was used to further reduce the number of coefficients of the MP-DPD by decreasing the nonlinearity orders in the different branches individually. These two steps allowed for a reduction of the number of coefficients to almost one-third and the conditioning number by three orders of magnitude while maintaining the same linearization capability. This substantially alleviates the requirements on the digital signal processors and the time needed to construct and implement the MP-DPD in real environment. Experimental validation carried out using a 400 Watt Doherty Power Amplifier (DPA), driven with 4-Carrier WCDMA signal, showed excellent linearization capability by achieving an ACPR of better than 50 dBcwith a power efficiency of better than 42.4%.