A single-chip FPGA implementation of the data encryption standard (DES) algorithm

Author

Wong, K. ; Wark, M. ; Dawson, E.

Author_Institution

Inf. Security Res. Centre, Queensland Univ. of Technol., Brisbane, Qld., Australia

Volume

2

fYear

1998

fDate

1998

Firstpage

827

Abstract

This paper describes a single-chip implementation of the data encryption standard (DES) using Xilinx XC4000 series field programmable gate array technology under the XACTstep design flow integration system. The implementation details for key scheduling, S-boxes, permutations and the round-function are described. The design process included schematic design, functional and timing simulation and design verification. The final design used 224 combinational logic blocks (CLBs) and 54 input/output blocks (IOBs) and has an encryption speed of 26.7 Mbps

Keywords

VLSI; circuit simulation; code standards; combinational circuits; cryptography; field programmable gate arrays; telecommunication standards; timing; 26.7 Mbit/s; DES algorithm; National Bureau of Standards; S-boxes; USA; VLSI; XACTstep design flow integration system; Xilinx XC4000 series; combinational logic blocks; data encryption standard; design process; design verification; encryption speed; field programmable gate array; functional simulation; input/output blocks; key scheduling; permutations; round-function; schematic design; single-chip FPGA implementation; timing simulation; Algorithm design and analysis; Cryptography; Field programmable gate arrays; Hardware; Information security; NIST; Process design; Processor scheduling; Programmable logic arrays; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1998. GLOBECOM 1998. The Bridge to Global Integration. IEEE

Conference_Location

Sydney,NSW

Print_ISBN

0-7803-4984-9

Type

conf

DOI

10.1109/GLOCOM.1998.776849

Filename

776849