Optimal pin-assignment for ground noise minimization in IC packages and connectors

Author

Lihong Zhang ; Zhang, Lihong

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

fYear

1996

fDate

28-31 May 1996

Firstpage

761

Lastpage

764

Abstract

With the rapid increase in operating frequency in today´s VLSI systems, signal integrity due to VLSI packages and interconnects becomes one of the critical factors in the overall design. This paper addresses the signal integrity based design optimization of packages and connectors by using simulated annealing and genetic algorithms. A 2-dimensional genetic algorithm is developed for 2-dimensional pin assignment. To indicate the effectiveness of the method, three examples are presented for ground noise minimization using 1 and 2-dimensional pin assignment optimization techniques. Both methods achieved signal integrity improvements under realistic running times

Keywords

integrated circuit packaging; 2D genetic algorithm; IC packages; VLSI packages; connectors; design optimization; ground noise minimization; interconnects; optimal pin-assignment; signal integrity; simulated annealing; Connectors; Design optimization; Frequency; Genetic algorithms; Integrated circuit noise; Integrated circuit packaging; Minimization methods; Signal design; Simulated annealing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1996. Proceedings., 46th

Conference_Location

Orlando, FL

ISSN

0569-5503

Print_ISBN

0-7803-3286-5

Type

conf

DOI

10.1109/ECTC.1996.550493

Filename

550493