DocumentCode
2947448
Title
A novel hardware acceleration technique for high performance parallel FDTD method
Author
Yu, Wenhua ; Yang, Xiaoling ; Liu, Yongjun ; Mittra, Raj
Author_Institution
EMC Lab, Pennsylvania State University, University Park, 16802, USA
fYear
2011
fDate
3-8 July 2011
Firstpage
3154
Lastpage
3157
Abstract
In this paper, we introduce one novel hardware acceleration technique based on a vector unit built in a regular CPU for high performance electromagnetic simulation. We investigate the performance of parallel FDTD method on the Intel and AMD processors accelerated by the Vector Arithmetic Logic Unit (VALU), high performance cluster, and Graphics Processing Unit (GPU). The FDTD method that is parallel in nature is one of the most popular numerical methods to simulate various electromagnetic problems and phenomena. Several examples are employed to demonstrate the engineering applications of parallel conformal FDTD method based on the VALU acceleration.
Keywords
Acceleration; Computer architecture; Finite difference methods; Graphics processing unit; Time domain analysis; Workstations; FDTD; SSE; VALU; hardware acceleration;
fLanguage
English
Publisher
ieee
Conference_Titel
Antennas and Propagation (APSURSI), 2011 IEEE International Symposium on
Conference_Location
Spokane, WA
ISSN
1522-3965
Print_ISBN
978-1-4244-9562-7
Type
conf
DOI
10.1109/APS.2011.5997202
Filename
5997202
Link To Document