FPGA-based LDPC Code Evaluation using an Advanced Magnetic Recording Channel Model

Low density parity check (LDPC) codes have shown near-capacity performance in additive white Gaussian noise channels. In magnetic recording systems, the readback signals suffer from various impairments in addition to additive noise. In this paper, we describe an FPGA-based advanced magnetic recording channel simulator and an LDPC coding system. Major magnetic recording channel impairments (namely, inter-symbol interference, transition noise, electronic noise, and media nonlinearities) are included in this model. The LDPC coded system is evaluated down to bit error rate (BER) of 10^-11 and frame error rate (FER) of 10^-8.