Integrated Single Event Latchup protection for ASICs used in space applications

Author

Petrovic, V. ; Ilic, Marija ; Schoof, G. ; Stamenkovic, Z.

Author_Institution

IHP, Frankfurt (Oder), Germany

fYear

2013

fDate

26-28 Nov. 2013

Firstpage

624

Lastpage

627

Abstract

The paper presents a protection technique for CMOS ASIC designs, based on the integrated Single Event Latchup (SEL) protection. Triple or double modular redundancy, together with integrated SEL protection switches (SPS) make the base for the fault-tolerant ASICs, able to operate in space environment. The presented approach represents a cheap solution, based on standard non-radiation hardened process. The SPS has been designed, characterized and verified in both standard and radiation environment. The proposed protection technique requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. The concept has been verified on silicon.

Keywords

CMOS integrated circuits; application specific integrated circuits; fault tolerance; radiation hardening (electronics); space vehicle electronics; switches; CMOS ASIC designs; SPS; design automation tools; double modular redundancy; fault-tolerant ASICs; integrated SEL protection switches; integrated single event latchup protection; layout generation; logic synthesis; nonradiation hardened process; space environment; triple modular redundancy; Application specific integrated circuits; CMOS integrated circuits; Power supplies; Radiation effects; Sensors; Standards; Transistors; ASIC design; Single event effect; fault tolerance; latchup protection switch; radiation effects; triple and double modular redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunications Forum (TELFOR), 2013 21st

Conference_Location

Belgrade

Print_ISBN

978-1-4799-1419-7

Type

conf

DOI

10.1109/TELFOR.2013.6716308

Filename

6716308