Title :
Chip design of phase-locked loop for ISM band applications
Author :
Huang, Jhin-Fang ; Li, Po-Ching ; Wen, Jiun-Yu ; Liu, Ron-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
Abstract :
A TSMC 0.35 um CMOS 2P4M process PLL (phase-locked loop) for ISM band applications is proposed. The PLL, with a crossed-coupled pMOS ring-oscillator VCO, is realized without using any inductor. Measurement results show that at the supply voltage of 3.3 V and the lowest reference frequency of 25 MHz, the locking range is from 1.8 GHz to 3.29 GHz, locking time is less than 3 us and the phase noise is -107.1 dBc/Hz at 1 MHz offset. The total power consumption of the PLL is 85.4 mW at center frequency of 2.48 GHz. The core chip area is only 0.17 mm2 and including pad, it is 1.02 mm2.
Keywords :
CMOS integrated circuits; integrated circuit design; phase locked loops; phase noise; voltage-controlled oscillators; CMOS 2P4M process; ISM band applications; PLL; chip design; core chip area; crossed-coupled pMOS ring-oscillator VCO; frequency 1.8 GHz to 3.29 GHz; frequency 25 MHz; locking range; locking time; phase noise; phase-locked loop; power 85.4 mW; power consumption; size 0.35 mum; voltage 3.3 V; CMOS process; Chip scale packaging; Frequency measurement; Inductors; Noise measurement; Phase locked loops; Phase measurement; Semiconductor device measurement; Time measurement; Voltage-controlled oscillators; PLL; VCO; phase-locked loop; voltage-controlled cscillator;
Conference_Titel :
Wireless Communications & Signal Processing, 2009. WCSP 2009. International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-4856-2
Electronic_ISBN :
978-1-4244-5668-0
DOI :
10.1109/WCSP.2009.5371414
