Mat-core: A matrix core extension for general-purpose processors

This paper proposes new processor architecture to exploit the increasingly number of transistors per integrated circuit and improve the performance of data parallel applications on general-purpose processors. The proposed processor (called Mat-core) is based on the use of multi-level ISA to explicitly communicate data parallelism to processor in a compact way instead of the dynamic extraction using complex hardware or the static extraction using sophisticated complier techniques. Since the fundamental data structures for data parallel applications are scalar, vector, and matrix data, Mat-core extends a scalar core (for executing scalar instructions) with a matrix unit (for executing vector/matrix instructions). Like vector microarchitectures, the extended matrix unit is organized in parallel lanes; each lane contains a pipeline of each functional unit and a slice of the register file. However, the Mat-core processor can effectively process not only vector but also matrix data on the parallel lanes. The increasingly budget of transistors can be exploited to scale the Mat-core processor by providing more cores in a physical package. On a multi-core processor, performance would be improved by parallel processing threads of codes using multi-threading techniques.