A novel random PWM technique with minimum computational overhead and constant sampling frequency for high-volume, low-cost applications

A novel random PWM technique for three-phase voltage-source inverters, characterized by a minimum computational overhead, a variable switching frequency, and a constant sampling frequency, is presented. The technique is based on two strategies: (1) the so-called arithmetic PWM (APWM), which yields the same switching patterns as the classic space-vector modulation, but with minimized computational effort, and (2) randomization of switching periods by variations of the delay of switching cycles with respect to corresponding sampling cycles. Simplicity of the technique, named a variable-delay random PWM (VDRPWM) method, allows its implementation in cheap, low-end processors. It makes the VDRPWM the best choke for high-volume low-cost applications, such as domestic and automotive AC drives and AC UPSs. The random aspect of the technique has a mitigating effect on the acoustic and electromagnetic noise emitted by the drive. This feature has been confirmed by experimental investigation of a 40-hp induction motor drive employing the VDRPWM.