Title :
2-D DWT/IDWT processor design for image coding
Author :
Xuyun, Chen ; Ting, Zhou ; Zhang Qianlin ; Hao, Min
Author_Institution :
State Key Lab., Shanghai, China
Abstract :
In this paper, a VLSI architecture for forward/inverse 2-D discrete wavelet transform is presented. This design described and verified by the VHDL is synthesized by the Synopsys-synthesizer. The synthesis results show that the gate-level circuit contains 7140 gates and the throughput can reach 4 M pixel/s when LSI 10 K CMOS process technology is used
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; hardware description languages; image coding; integrated circuit design; inverse problems; wavelet transforms; 2D discrete wavelet transform; LSI CMOS technology; Synopsys; VHDL synthesis; VLSI architecture; gate-level circuit; image coding; inverse 2D discrete wavelet transform; processor design; Circuit synthesis; Discrete wavelet transforms; Finite impulse response filter; Image coding; Multiresolution analysis; Process design; Signal processing; Synthesizers; Very large scale integration; Wavelet transforms;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562764
