VLSI design for a new adaptive image compress coding

Author

Ke, Jiang ; Yan, Ding Bao ; Ling, Zhang Qian

Author_Institution

ASIC & Syst. Lab., Fudan Univ., Shanghai, China

fYear

1996

fDate

21-24 Oct 1996

Firstpage

119

Lastpage

122

Abstract

This paper presents a new adaptive classified image coding which combine the high-compression ratio of vector quantization and edge-preserving ability of BTC. The VLSI design for this algorithm is described too. In our design, the parallel-pipeline architecture is adopted for closest codeword searching, and mean absolute error scheme is used as distortion measure in order to reduce the scale of circuit

Keywords

VLSI; adaptive codes; data compression; digital signal processing chips; image coding; integrated circuit design; BTC; VLSI design; adaptive image compress coding; algorithm; closest codeword searching; compression ratio; distortion measurement; edge preservation; mean absolute error; parallel-pipeline architecture; vector quantization; Adaptive coding; Algorithm design and analysis; Application specific integrated circuits; Bit rate; Decoding; Degradation; Distortion measurement; Image coding; Vector quantization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562766

Filename

562766

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2948901