DocumentCode
2949297
Title
A novel VLSI design for survivor memory unit in Viterbi decoder
Author
Han, Yan
Author_Institution
State Key CAD&CG Lab., Zhejiang Univ., Hangzhou, China
fYear
1996
fDate
21-24 Oct 1996
Firstpage
127
Lastpage
130
Abstract
Since Viterbi Decoder (VD) plays an important role in the realization of HDTV and other digital systems, many efforts have been made on the research and development of the integration of VDs. Survivor Memory Unit (SMU) is one of the three major units which consist of a Viterbi decoder. A novel VLSI approach for realizing SMU differing from the traditional technique is proposed in this paper. A rate=4/5, v=3, L=15, 32 QAM Viterbi decoder with this new structure has been designed and passed the computer simulation
Keywords
VLSI; Viterbi decoding; integrated circuit design; integrated memory circuits; HDTV; VLSI design; Viterbi decoder; computer simulation; digital system; integration; survivor memory unit; Buffer storage; CMOS technology; Circuits; Decoding; Delay; Hardware; Random access memory; Registers; Very large scale integration; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562768
Filename
562768
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