A multiprocessor architecture for fast packet processing

The design of high performance application-specific processors is the bottleneck in many applications. In critical high data rate network devices such as modems and other end-user interfaces, the packet forwarding engine requires both high degree of flexibility (to support large number of protocols) as well as extremely high performance (to be able to support Gigabit processing). While hardware application-specific designs can cope with performance, they lack flexibility. Although software based solutions could be ideal to meet flexibility and low cost constraints, unfortunately, they miss the speed performance requirement. The main goal of this paper is to present an architectural model to design a new processor architecture based on multiple cores and specific dedicated hardware units. In particular, we propose a new model which takes into account network protocols characteristics and input traffic nature to meet performance and cost requirements.