Title :
Implementation of very low bitrate video encoder core
Author :
Miyanohana, Koji ; Fujita, Gen ; Onoye, Takao ; Shirakawa, Isao
Author_Institution :
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
Abstract :
A very low bitrate video encoder core developed. A new mechanism is devised so as to seek horizontal and vertical edges simultaneously, which can achieve a high throughput for an edge detector. A new scheme is also introduced into the PE (Processing Element) array so as to be shared by an vector quantizer and a motion estimator. Owing to these sophisticated concepts, specific functional macrocells have been implemented for the encoder core in the total area of 55.3 mm2 by a 0.6 μm triple-metal CMOS technology
Keywords :
CMOS digital integrated circuits; digital signal processing chips; edge detection; motion estimation; vector quantisation; video coding; 0.6 micron; edge detector; macrocell; motion estimator; processing element array; triple-metal CMOS technology; vector quantizer; very low bitrate video encoder core; Bandwidth; Bit rate; CMOS technology; Detectors; Discrete cosine transforms; Encoding; Motion estimation; Standardization; Transform coding; Very large scale integration;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562769
