Statistical error analysis of VLSI architectures: methodology and a case study

A methodology is presented for the statistical analysis of the arithmetic error of VLSI architectures. Attention is focused on predicting the arithmetic errors of the overall architecture as a function of register lengths, the type of word representations used, and the precision of the arithmetic blocks (adder/subtracters, multipliers, shifters, dividers, etc.). The methodology is demonstrated by application to a newly developed for use in a large-scale signal processing wafer architecture, a L-U decomposition array. The wafer design, intended for radar signal processing, is part of an ongoing effort on restructurable wafer-scale integration for large-scale signal processing