DocumentCode :
2950267
Title :
Floorplan-aware Steiner tree reconstruction for optimal buffer insertion
Author :
Yan, Jin-Tai ; Lee, Chia-Fang ; Wang, Tzu-Ya
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Chung Hua Univ., Hsinchu
fYear :
2005
fDate :
11-14 Dec. 2005
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, based on the information of blockages and empty space in a given floorplan, any Steiner tree must be reconstructed to avoid the routing over the blockages by using detour-path modification and increase the opportunity of inserting buffers in the Steiner tree by using Steiner-point or routing-path modification. The experimental results show that the optimal buffer insertion with our proposed floorplan-aware Steiner tree reconstruction can obtain 8%~15% delay improvement than that without any floorplan-aware Steiner tree reconstruction for the tested Steiner trees on a given floorplan.
Keywords :
buffer circuits; integrated circuit layout; network routing; trees (mathematics); Steiner tree reconstruction; buffer insertion; delay improvement; detour-path modification; floorplanning; routing-path modification; Computer science; Delay; Minimization methods; Pins; Routing; Silicon; Steiner trees; Testing; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-9972-61-100-1
Electronic_ISBN :
978-9972-61-100-1
Type :
conf
DOI :
10.1109/ICECS.2005.4633438
Filename :
4633438
Link To Document :
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