ASAP: an asynchronous array processor for hardware-software coprocessing and codesign

Traditional field programmable gate arrays (FPGAs) originate and are used to prototype digital designs. Recently, there has been increasing interest in using FPGAs as attached systems for hardware-software coprocessing and codesign. However, existing FPGAs on the market all implement general purpose logic designs. They are not well defined for the coprocessing and codesign purpose. In this paper, an analysis and comparison of existing FPGA architectures against requirements from synthesis process on algorithm specifications is described. Based on this analysis, the design of a configurable ASynchronous Array Processor (ASAP) and the development of a data-driven multiple thread computation model for the processor are presented. The system´s performance is data dependent and measured by average instead of worst cases in synchronous FPGAs. The ASAP easily out-performs other coprocessing systems as a frame buffer by embedding a fast forward difference polynomial evaluation algorithm