DocumentCode :
2950370
Title :
Fast complete memory consistency verification
Author :
Chen, Yunji ; Lv, Yi ; Hu, Weiwu ; Chen, Tianshi ; Shen, Haihua ; Wang, Pengyu ; Pan, Hong
Author_Institution :
Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing
fYear :
2009
fDate :
14-18 Feb. 2009
Firstpage :
381
Lastpage :
392
Abstract :
The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new natural partial order: time order. In multiprocessor systems with store atomicity, a time order restriction exists between two operations whose pending periods are disjoint: the former operation in time order must be observed by the latter operation. Based on the time order restriction, memory consistency verification is localized: for any operation, both inferring related orders and checking related cycles need to take into account only a bounded number of operations. Our method has been implemented in a memory consistency verification tool for CMP (chip multi processor), named LCHECK. The time complexity of the algorithm in LCHECK is O(Cpp2n2) (where C is a constant, p is the number of processors and n is the number of operations) for soundly and completely checking, and O(p3n) for soundly but incompletely checking. LCHECK has been integrated into both pre and post silicon verification platforms of the Godson-3 microprocessor, and many bugs of memory consistency and cache coherence were found with the help of LCHECK.
Keywords :
computational complexity; memory architecture; microprocessor chips; optimisation; silicon; Godson-3 microprocessor; LCHECK; NP-hard; chip multi processor; fast complete memory consistency verification; multiprocessor systems; natural partial order; silicon verification platforms; store atomicity; time complexity; time order; time order restriction; Algorithm design and analysis; Computer bugs; Costs; Microarchitecture; Microprocessors; Multiprocessing systems; Observability; Polynomials; Silicon; Testing; cache coherence; memory consistency; pending period; time order; verification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on
Conference_Location :
Raleigh, NC
ISSN :
1530-0897
Print_ISBN :
978-1-4244-2932-5
Type :
conf
DOI :
10.1109/HPCA.2009.4798276
Filename :
4798276
Link To Document :
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