A dual token ring and Ethernet LAN interface chip

Author

Co, Ramon S. ; Yang, Howard C. ; Haung, Haw-Ming

Author_Institution

Kingston Technol. Corp., Fountain Valley, CA, USA

fYear

1996

fDate

21-24 Oct 1996

Firstpage

167

Lastpage

170

Abstract

A CMOS LAN interface chip that combines the physical layer functions for both the token ring and Ethernet networks is described. The 4/16 mbps Token Ring interface exceeds the jitter tolerance (0.5 ns/UI) and accumulated phase slope (0.25 ns/UI) requirements at 16 Mbps of the IEEE 802.5 draft standard for STP/UTP transmission media. The 10 Mbps Ethernet interface supports both the AUI and 10BaseT functions of the IEEE 802.3 standard

Keywords

CMOS digital integrated circuits; application specific integrated circuits; data communication equipment; jitter; local area networks; network interfaces; telecommunication standards; token networks; transport protocols; 10BaseT functions; 4 to 16 Mbit/s; ASIC; AUI functions; CMOS interface chip; Ethernet LAN; IEEE 802.3 standard; IEEE 802.5 draft standard; LAN interface chip; STP/UTP transmission media; dual protocol interface chip; jitter tolerance; physical layer functions; token ring LAN; Clocks; Detectors; Ethernet networks; Jitter; Local area networks; Phase detection; Phase locked loops; Protocols; Token networks; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562778

Filename

562778