Title :
Using synthesis, simulation, and hardware emulation to prototype a pipelined RISC computer system
Author :
Hamblen, James O.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper describes a VHDL based rapid prototyping approach to simulate, synthesize, and implement a prototype computer system using commercial CAD tools, a meta assembler, a retargetable C compiler, and FPGAs in a hardware emulator. This methodology is utilized in a senior design laboratory sequence of two required courses for computer engineering students at Georgia Tech
Keywords :
computer science education; hardware description languages; high level synthesis; pipeline processing; reduced instruction set computing; software prototyping; C compiler; CAD tool; FPGA; VHDL; computer engineering education; hardware emulation; meta assembler; pipelined RISC computer system; rapid prototyping; simulation; synthesis; Assembly systems; Computational modeling; Computer simulation; Design automation; Emulation; Engineering students; Field programmable gate arrays; Hardware; Laboratories; Virtual prototyping;
Conference_Titel :
Microelectronic Systems Education, 1997. MSE '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Arlington, VA
Print_ISBN :
0-8186-7996-4
DOI :
10.1109/MSE.1997.612580
