A fully synthesizable parameterized Viterbi decoder

Author

Burger, R. ; Cesana, G. ; Paolini, M. ; Turolla, M. ; Vercelli, S.

Author_Institution

STMicroelectron., Agrate Brianza, Italy

fYear

1999

fDate

1999

Firstpage

27

Lastpage

30

Abstract

The Viterbi algorithm is widely used in digital communications. It realizes the maximum-likelihood decoding of convolutional codes received from a noisy channel. Depending on the application (terrestrial, digital modems, digital cellular telephone applications and others) a Viterbi decoder must be designed to respect specific requirements such as small area, high speed or maximum efficiency. This paper presents a parameterized implementation of this algorithm for design reuse purposes, in order to allow the implementation of the most optimized solution for each application, exploiting input parallelism, sharing the ACS units, adjusting depth of computation and BER computation

Keywords

CMOS digital integrated circuits; Viterbi decoding; circuit CAD; convolutional codes; digital signal processing chips; error statistics; integrated circuit design; maximum likelihood decoding; ACS units sharing; BER computation; Viterbi algorithm; Viterbi decoder; bit error rate; convolutional codes; design reuse; fully synthesizable decoder; input parallelism; maximum-likelihood decoding; parameterized implementation; Algorithm design and analysis; Concurrent computing; Convolutional codes; Design optimization; Digital communication; Maximum likelihood decoding; Modems; Parallel processing; Telephony; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777237

Filename

777237