Hierarchical watermarking for protection of DSP filter cores

A hierarchical watermarking approach is developed that incorporates an ownership identification directly into the design development process. This approach offers a high degree of tamper resistance and provides easy, noninvasive copy detection. We present two FIR digital filter cores, one watermarked at the algorithm level and the second at the algorithm and architecture levels. A unique ownership signature (watermark) is placed at each level. At the algorithm level, the watermark is embedded in the filter coefficients during the development of the transfer function. At the architecture level, we use circuit transformations to watermark the design. Experimental results show approximately 7% area overhead of the algorithm-level watermarked design over a non-watermarked design. The cost of area for the design watermarked at both the algorithm and architecture levels is less than 40%