A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

Author

Kurohmaru, S. ; Matsuo, M. ; Nakajima, H. ; Kohashi, Y. ; Yonezawa, T. ; Moriiwa, T. ; Ohashi, M. ; Toujima, M. ; Nakamura, T. ; Hamada, M. ; Hashimoto, T. ; Fujimoto, H. ; Iizuka, Y. ; Michiyama, J. ; Komori, H.

Author_Institution

Div. of Corp. Semicond. Dev., Matsushita Electr. Ind. Co. Ltd., Fukuoka, Japan

fYear

1999

fDate

1999

Firstpage

69

Lastpage

72

Abstract

We have developed a programmable DSP for MPEG4, H.263, H.261 and wavelet based sub-band codec algorithms. This DSP has the capability of processing these algorithms in real-time and has excellent flexibility, so that it can, for instance, perform video codec at 15 CIF frames/sec or video/speech (G.723.1) codec at 30 QCIF frames/sec. This chip includes a video pre/post-processing engine and needs only one 16 Mbit SDRAM as an external memory to perform the above algorithms, making it possible to realize low-cost systems. This chip is fabricated using 0.25 um CMOS technology and contains 7.7 M transistors on 9.41 mm×9.22 mm die

Keywords

CMOS digital integrated circuits; digital signal processing chips; embedded systems; programmable circuits; video codecs; wavelet transforms; 0.25 micron; CMOS DSP chip; MPEG4 programmable codec; SDRAM memory; embedded post-processing engine; embedded pre-processing engine; real-time processing; speech codec; video codec; wavelet subband algorithm; Arithmetic; Digital signal processing; Digital signal processing chips; Engines; MPEG 4 Standard; Noise reduction; Performance evaluation; SDRAM; Speech codecs; Video sharing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777245

Filename

777245