DocumentCode
2951335
Title
A low-power single-chip MPEG-2 CODEC LSI
Author
Tsuboi, Yukitoshi ; Arai, Hideo ; Takahashi, Masaru ; Oku, Masuo
Author_Institution
Syst. LSI Dev. Center, Hitachi Ltd., Japan
fYear
1999
fDate
1999
Firstpage
73
Lastpage
76
Abstract
A single-chip MPEG-2 CODEC LSI design has been completed. The “CODEC” functions, i.e. both encoding and decoding functions, are provided. This LSI is being fabricated in a 0.18 μm CMOS technology. Small chip size and low power consumption less than 500 mW are expected. This LSI is fully synthesizable from RTL source codes written in Verilog-HDL and easily adaptable to various IP (Intellectual Property) blocks
Keywords
CMOS digital integrated circuits; data compression; industrial property; integrated circuit design; large scale integration; video codecs; video coding; 0.18 micron; CMOS technology; CODEC; LSI; MPEG-2; RTL source codes; Verilog-HDL; chip size; decoding functions; encoding functions; intellectual property blocks; power consumption; CMOS technology; Clocks; Codecs; DVD; Decoding; Encoding; Energy consumption; Frequency; Large scale integration; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location
San Diego, CA
Print_ISBN
0-7803-5443-5
Type
conf
DOI
10.1109/CICC.1999.777246
Filename
777246
Link To Document