SRSL pipelining of coarse-grain datapaths

In this paper, we propose a clockless handshake mechanism based on self-resetting stage logic targeted for pipelined datapaths. In this logic, a stage resets itself after it completes the evaluation of its embedded logic. As such, a stage oscillates between a reset phase and an evaluate phase thus completing a single period. This handshake mechanism is incorporated into two distinct pipelines where its coordination is limited to each pair of neighboring stages in the first pipeline, while it is driven by the last stage in the second pipeline. Implementation results of both pipelines show that they can reach throughputs of several hundred Mega outputs per second, while they can easily reach the 1.4 Giga outputs per second if implemented as FIFOs.